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| AN159 Application Note PLL FILTER OPTIMIZATION FOR THE CS8415A, CS8420, AND CS8427 by Patrick Muyshondt and Stuart Dudley Dimond III 1. INTRODUCTION The purpose of this application note is to give users of the CS8415A, CS8420, and CS8427 the information needed to optimize the performance of the Phase-Locked Loop for their requirements. Equations are provided to determine the filter values when driving the PLL from the AES Receiver or from the Serial Input Port. The PLL design of the CS8415A, CS8420, and CS8427 is different from that of the CS8411/12 and CS8413/14. The filter values computed by the equations in this applications note are not applicable to the older devices. The sections on capacitor choice and board layout are applicable to both the old and the new parts. 2. PLL SYSTEM PARAMETERS Figure 1 is a simplified diagram of the PLL in these parts. When the PLL is locked to an AES3 input stream, it is updated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, FS. When the PLL is locked to ILRCK, it is updated at FS so that the duty cycle of the input doesn't affect jitter. The following operating parameters of the PLL system are used in the filter calculations: VCO Gain: KVCO = 4 MHz/V Charge Pump Current: ICP = 300 A Divider for AES3: N = 128 Divider for ILRCK: N = 256 INPUT Phase Comparator and Charge Pump VCO Rfilt Cfilt Crip RMCK /N Figure 1. PLL Block Diagram P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com Copyright Cirrus Logic, Inc. 1999 (All Rights Reserved) DEC `99 AN159REV1 1 AN159 3. CAPACITOR CHOICE Users frequently ask what capacitors to select for the PLL filter. Large or exotic film capacitors are not necessary. Their leads and the longer circuit board traces they require add undesirable inductance to the circuit. Surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the FILT pin to minimize trace inductance. For CRIP, a C0G or NPO dielectric is recommended, and for CFILT, an X7R dielectric is preferred. Avoid capacitors with large temperature coefficients, or capacitors with high dielectric constants, that are sensitive to shock and vibration. These include the Z5U and Y5V dialectrics. minimize the inductance in the filter path. The VA+ and AGND traces extend back to their origin and are shown only in truncated form in the drawing. 5. PLL DESIGN EQUATIONS The following equations provide a loop phase margin of 60. This has been tested in the lab and found to be optimum. It gives the best performance in tolerating jitter on the incoming signal and maximizes DAC THD+N performance. Jitter transfer function peaking is 0.74 dB with the given equations (EQ1, EQ2, EQ3, EQ4, EQ6, and EQ8). The AES3 standard permits a maximum jitter peaking of 2 dB. The IEC60958 consumer specification allows a maximum of 3 dB of jitter peaking. To use the design equations, first determine the minimum sample frequency that the PLL will have to lock to. If you are using only the AES receiver use the equations in the AES3 design example. If you are using the Input Serial Port or the Input Serial Port and the AES Receiver, use the equations in the Serial Input Port design example. 4. BOARD LAYOUT Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure 2 contains a suggested layout for the PLL filter components and for bypassing the analog supply voltage. The 0.1 F bypass capacitor is in a 1206 form factor. RFILT and the other three capacitors are in an 0805 form factor. The traces are on the top surface of the board with the IC so that there is no via inductance. The traces themselves are short to AGND 1000 pF Crip Rfilt .1F Cfilt Figure 2. Recommended Layout Example 2 FILT VA+ AN159REV1 AN159 5.1 AES3 Design Example Assume an application in which the incoming AES3 stream may have a sample rate from 32 kHz to 96 kHz. Using the minimum FS of 32 kHz, the following can be computed: f 32000 f pole = --s = -------------- = 16000 2 2 f 32000 f lpbw = --s = -------------- = 8000 4 4 fs f zero = ----- = 32000 = 400 -------------80 80 EQ 1 EQ 2 EQ 3 2 128 8000 ----------------------------------------- = 5362 -6 6 300 x10 4 x10 EQ 5 Select RFILT = 5100 Ohms, the nearest standard 5% value. 1 --------------------------------------- = C FILT 2 R FILT f zero -6 1 ----------------------------------- = 0.078 x10 2 5100 400 EQ 6 EQ 7 Select CFILT = 0.082 F, the nearest standard value. 1 --------------------------------------- = C RIP 2 R FILT f pole EQ 8 With these values the filter components can then be determined. 2 N f lpbw ------------------------------ = R FILT I CP K VCO EQ 4 -9 1 ----------------------------------------- = 1.95 x10 EQ 9 2 5100 16000 Select CRIP = 2.2 nF, the nearest standard value. Fs 96 kHz 88.2 kHz 48 kHz 44.1 kHz 32 kHz 24 kHz 16 kHz 8 kHz RFILT 16k 15k 8.2k 7.5k 5.1k 3.9k 2.7k 1.3k CFILT 8.2 nF .01 F .033 F .039 F .082 F .15 F .33 F 1.2 F CRIP 220 pF 270 pF 820 pF 1000 pF 2200 pF 3900 pF 8200 pF .033 F Table 1. Pre-computed values for operation from an AES3 input AN159REV1 3 AN159 5.2 Serial Input Port Design Example Assume an application in which the Input Serial Port is driven at a sample rate of 32 kHz. The following can be computed: f f pole = --s = 32000 = 8000 -------------4 4 f lpbw f zero f = --s = 32000 = 4000 -------------8 8 fs = -------- = 32000 = 200 -------------160 160 EQ 10 EQ 11 EQ 12 1 --------------------------------------- = C RIP 2 R FILT f pole -9 1 -------------------------------------- = 3.90 x10 2 5100 8000 2 256 4000 ----------------------------------------- = 5362 -6 6 300 x10 4 x10 EQ 14 Select RFILT = 5100 Ohms, the nearest standard 5% value. 1 EQ 15 --------------------------------------- = C FILT 2 R FILT f zero -6 1 ----------------------------------- = 0.156 x10 2 5100 200 EQ 16 Select CFILT = 0.15 F, the nearest standard value. EQ 17 EQ 18 With these values the filter components can then be determined. 2 N f lpbw ------------------------------ = R FILT I CP K VCO EQ 13 Select CRIP = 3.9 nF, the nearest standard value. Fs 96 kHz 88.2 kHz 48 kHz 44.1 kHz 32 kHz 24 kHz 16 kHz 8 kHz RFILT 16k 15k 8.2k 7.5k 5.1k 3.9k 2.7k 1.3k CFILT .018 F .022 F .068 F .082 F .15 F .27 F .68 F 2.7 F CRIP 390 pF 560 pF 1800 pF 2200 pF 3900 pF 6800 pF .015 F .062 F Table 2. Pre-computed values for operation from ILRCK or from ILRCK and AES3 4 AN159REV1 * Notes * |
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